In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge (or capacitance) in spite of parasitic capacitance and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
Storage cells formed with hemispherical grain polysilicon gains unique advantages as the hemispherical grain polysilicon enhances the surface area of a storage cell electrode without any additional complex processing. However, conventional methods of forming HSG polysilicon by deposition, develop roughness of the polysilicon which starts at the interface of the polysilicon and forms towards its surface. It is desirable to have the roughness of the polysilicon develop by starting at the polysilicon surface and continue to form towards the polysilicon's interface. The present invention develops such a technique.
U.S. Pat. No. 5,162,248, and U.S. Pat. No. 5,340,765, having the same assignee as does the present invention, are hereby incorporated by reference.